Error detection and correction (EDC) techniques may be used in electronic systems to detect and correct errors that arise during memory accesses. These techniques typically operate by storing a data word along with an associated error correcting code (ECC). ECCs can be communicated to and from a memory device by communicating ECCs spatially in parallel with data signals via wider datapaths, by temporally multiplexing ECCs with data signals via shared datapaths, or by some combination of these approaches, which may require additional memory for ECC storage. As a result, a non-power-of-2 memory size may be required. To implement temporal multiplexing, the memory system bandwidth will be degraded by the fraction of bandwidth consumed by ECCs. This degradation of memory system bandwidth can be further aggravated by inefficiencies related to the scheduling of memory transactions involving ECCs.
Table 1 illustrates different scenarios for routing a data access address RA[10:0] and an ECC access address ECC[10:0] onto different partitions of a memory bank based on a two-bit selection signal RA[12:11].